The present invention relates to a multi-processing system and a cache apparatus employed in the system.
There has been known a processing system in which, in order to match the machine cycle time of a processor with an operating time of a main memory, a cache memory operating with a high-speed is disposed between the processor and the main memory so as to improve the system efficiency. Heretofore, as a store method for a cache, there have been employed a write-through method and a copy-back method as described in the "ACM, Computing Surveys", Vol. 14, No. 3, September 1982, pp. 500-502.
In the write-through method, in a case where a processor conducts a write operation, if a hit occurs in the cache, the write operation is accomplished both in the cache and in the main memory such that the contents of the cache are consistent with those of the main memory in all situations.
In contrast, according to the copy-back method, if a hit occurs in the cache, the write operation is accomplished only in the cache, namely, data is not written in the main memory.
Comparing the write-through method with the copy-back method, the control operation of the copy-back method is more complicated and hence requires a larger amount of hardware, which is emphasized particularly in a control operation employed in a multi-processing system of a shared memory type to retain consistency of the contents of each cache. An example of the copy-back method has been described, in Japanese Patent Publication No. 51-49535 which corresponds to U.S. patent application Ser. No. 179,376 filed on Sep. 10, 1971.
However, with respect to the performance, in the copy-back method, when a hit occurs in a cache, no write operation is carried out in the main memory; consequently, the write time of the main memory write operation can be dispensed with and hence the copy-back method is advantageous as compared with the write-through method in this regard. Furthermore, because the write time required to effect a write operation in the main memory is eliminated, there appears an advantage that the throughput required for the main memory is minimized. In a multi-processing system, the decrease of the memory throughput is particularly important to increase the system efficiency.
On the other hand, the U.S. Pat. No. 4,264,953 has disclosed a multi-processing system comprising a main memory, a plurality of processors communicating with the main memory, a plurality of cache memories corresponding to the plural processors, a plurality of address translators for translating virtual addresses (logical addresses) from the plural processors into physical addresses, and an input/output device.
In the system of the U.S. Pat. No. 4,264,953, in a case where data of a shared region of the main memory is stored in a cache, in order to avoid the problem of the data stored in the cache not corresponding to update data in the shared region of the main memory, an operation to copy the data of the shared region of the main memory into the cache is inhibited. On the other hand, in a case where data of the input/output device is stored in a cache, in order to avoid the problem of the data stored in the cache not being consistent with update data of the input/output device, the data of the input/output device is invalidated (purged) in the cache.
However, in the system described in U.S. Pat. No. 4,264,953, it may be assumed that the write-through method is adopted, and there has not been any indication related to a compatible employment of characteristics of both of the methods, namely, the write-through and copy-back methods.